1. Field of the Invention
The present invention generally relates to generating frequency signals, and more particularly to a system and method for controlling a frequency signal generator such as a phase lock loop.
2. Background of the Related Art
Phase locked loops (PLLs) are used in many wireless systems to perform digital clock synchronization, frequency synthesizing, and other functions. FIG. 1 shows a PLL which has been used in communication systems. This PLL includes a phase/frequency detector (PFD) 102, a charge pump and loop filter 104, a voltage-controlled oscillator (VCO) 106, and an optional frequency divider 108 situated along a feedback loop between the VCO and PFD.
In operation, the PFD compares phases or frequencies of input and output signals and then generates an UP or DOWN signal. If the comparison indicates the input signal is leading the output signal, the DOWN signal is generated. Conversely, the UP signal is generated if the input signal is lagging the output signal. Using the signal output from the PFD, the charge pump and loop filter generate a control signal Vcontrol for setting the output frequency of the VCO. This output frequency is then divided and fed back into the PFD for subsequent comparisons with the input signal. Through this feedback loop, the PLL is therefore able to “lock on” to a desired output frequency.
In many PLL applications, inductor-capacitor VCOs (LC-VCOs) are used because of their ability to demonstrate improved jitter/phase noise performance compared with other VCOs such as ring oscillators. To maintain a desired level of performance, LC-VCOs must be tuned to account for process variations that produce tolerances for the inductor and capacitor and to cover a required frequency range.
FIG. 2 shows one type of LC-VCO which has been proposed. This VCO includes two cross-coupled CMOS inverters. The first inverter is formed from PMOS transistor 202 and NMOS transistor 204, and the second inverter is formed from PMOS transistor 206 and NMOS transistor 208. The inverters are cross-coupled by connecting the common drain of the first inverter to the common gate of the second inverter and vice versa. The cross-coupled inverters thus form a multivibrator circuit.
The VCO also includes an LC circuit connected between the common drains A and B of the inverters. The LC circuit includes an inductor 210 connected in parallel to two varactors 211 and 212. Each varactor behaves as a reverse-biased diode having a junction capacitance which varies according to an applied voltage. When connected to the cross-coupled inverters, the resulting circuit forms an a stable multivibrator or a free running oscillator, where the free running frequency of the oscillator is the resonant frequency of the parallel LC circuit.
When it is desired to adjust the frequency of the oscillator, the two varactors are connected to the inductor to form an external or on-chip tank circuit 215. When a control voltage Vc is applied to the common cathode of the varactors, the dc voltage across the varactors changes. This causes the capacitance of the varactors to change and proportionally the output frequency of the oscillator. The oscillator frequency may be output from either of nodes A or B.
The FIG. 2 circuit has a number of drawbacks which limit performance. For example, while the varactors may be used to adjust the output frequency of the VCO, the adjustments tend to be slow, inaccurate, and one-dimensional. This, in turn, prevents a phase-locked loop incorporating the circuit from achieving fast-lock times. Also, the varactors in FIG. 2 are relatively large in size, which significantly diminishes the ability to reduce phase noise in the circuit.
In view of the foregoing, it is apparent that a need exists for a system and method for adjusting the output frequency of a voltage-controlled oscillator with greater speed and accuracy than other methods which have been proposed, and which achieves this improved accuracy while simultaneously providing multiple levels of frequency adjustment. There is also a need for a frequency generator (e.g., a phase-locked loop) which achieves faster lock times through the use of smaller-sized varactors which promote phase noise reduction as well as other performance improvements.